The invention relates to a semiconductor component with passivation layer.
Semiconductor components are generally provided with a passivation layer in order to minimize the influences of the environment, for example temperature fluctuations or moisture, on the semiconductor components. The passivation layer may furthermore serve for mechanical stabilization of the semiconductor components.
If a semiconductor component with passivation layer is exposed to severe temperature fluctuations, then cracks may arise in the passivation layer on account of different coefficients of thermal expansion of the passivation layer and of regions of the semiconductor component which adjoin the passivation layer. This is the case, for example, when the semiconductor component is closed off toward the outside by a molding compound adjoining the passivation layer, since the coefficients of thermal expansion of the passivation layer and the molding compound may deviate greatly from one another. If a crack arises within a critical region of the semiconductor component, for example in a region that insulates two conductive regions from one another, then the crack may lead to the impairment of the functioning of the semiconductor component. In the worst case, the cracking leads to a total failure of the semiconductor component.
The problem area described above is explained by way of example in the description below with reference to FIGS. 1 to 3.
FIG. 1 illustrates a cross section through a detail from a typical power semiconductor component. Arranged on a semiconductor body 1, which includes silicon in this embodiment, is a metal/insulation structure 2, which is in turn covered by a passivation layer 3. A buffer layer 4 is provided on the passivation layer 3, a molding compound layer 5, which functions as housing termination, in turn being arranged on said buffer layer. In this embodiment, the metal/insulation structure 2 has a first to third metal plane 6, 7 and 8, which are electrically connected to one another by conductive connections 9. The metal planes 6, 7, 8 are divided into different metal plane regions (in this embodiment, the first metal plane 6 is divided into five metal plane regions 61-65, and the second and third metal planes 7, 8 are divided into in each case three metal plane regions 71-73 and 81-83, respectively) which are electrically insulated from one another by insulation structures 10.
Since the coefficients of thermal expansion of the passivation layer 3 and the molding compound layer 5 generally turn out to be greatly different, great tensile forces oriented in the lateral direction occur at the transition between the passivation layer 3 and the buffer layer 4 in the event of temperature fluctuations, which is indicated by the arrows 11 illustrated in FIG. 2. If the tensile stresses exceed specific threshold values, then cracks 12 arise within the passivation layer 2. The cracks 12 arise in particular in regions of the passivation layer 3 which adjoin edges 13 of the topmost metal plane (third metal plane 8).
FIG. 3A illustrates a micrograph of a region from FIG. 2 which is identified by reference numeral 15. A crack 12 can clearly be seen, said crack having formed at an edge 13 of the metal region 82 within the passivation layer 3. The crack 12 illustrated in FIG. 3A is noncritical since moisture cannot pass into the semiconductor body 1 or into insulating intermediate regions (insulation structure 10) via said crack.
The situation proves to be more critical in a case such as is illustrated in FIG. 3B. FIG. 3B illustrates a plan view of a semiconductor component with a metallization 16. The metallization 16 is pervaded or interrupted by insulating regions 17. A passivation layer (transparent here) is provided above the metallization 16 and the insulating regions 17, cracks 12 having arisen in said passivation layer due to thermal stress. The cracks 12 run above the insulating regions 17 and thus constitute a risk that has to be taken seriously since proper insulation between the individual regions of the metallization 16 or between conductive regions lying below the metallization is no longer ensured on account of the cracks 12.